1. Field of the Invention
The present invention relates to a Silicon-On-Insulator (SOI) CMOS circuit provided with a plurality of PMOS transistors connected in series to each other.
2. Description of the Prior Art
Large-scale integration or LSI circuits have grown continually more powerful. Researches into integrating a more huge number of components on a single chip and speeding up LSI circuits have been ongoing. These researches have resulted in increases in power dissipation in LSI circuits. Some of the latest microprocessors consume tens of watts of power. Such increases in power dissipation in LSI circuits cause the following problems. The first problem is that heat internally generated in a chip has a deleterious effect on the reliability of the chip. The second problem is that a measure directed toward the dissipation of the internally generated heat, such as a cooling fan, causes an increase in the cost of manufacturing the chip. The third problem is that mobile information terminal equipment employing such high power LSI circuits is not easy-to-use because battery life is short. Thus the urgent challenge for manufactures, as well as users"" desire, is to reduce the power dissipation in LSI circuits while maintaining their performance.
The most effective measure of reducing the power dissipation in an LSI circuit is to reduce the power supply voltage. However, a reduction in the power supply voltage causes a reduction in the response performance of MOS transistors included in the LSI circuit and hence a reduction in the operating speed of the LSI circuit. Various measures directed toward the prevention of reduction in the operation speed of LSI circuits caused by reduction in the power supply voltage have been taken. Recently silicon-On-Insulator (SOI) CMOS circuits have captured much of the spotlight as such the measures.
SOI CMOS circuits provide three advantages as follows. The first advantage is that SOI CMOS circuits have low parasitic capacitance because they have a buried oxide film, resulting in reduction in the time required for charging and discharging a load and hence increases in the circuit speed, as disclosed in lines 2 through 8 on the right column of pp. 1106 of xe2x80x9cResearch and development trends of SOI technologyxe2x80x9d, Journal of Applied Physics Society of Japan, Vol. 64, No. 11, pp. 1104-1110, 1995. In other words, the first advantage is that even though a measure is taken to reduce the power supply voltage applied to an SOI CMOS circuit, the circuit speed can be maintained as it is high.
The second advantage is that even though a measure is taken to reduce the power supply voltage applied to an SOI CMOS circuit, the switching speed of MOS transistors is not reduced because the threshold voltages of the MOS transistors do not increase by virtue of the bias potential of their substrates, as disclosed in lines 23 through 33 on the right column of pp. 1106 of the above reference. Accordingly, even though a measure is taken to reduce the power supply voltage applied to an SOI CMOS circuit, the circuit speed can be maintained as it is high.
The third advantage is that the current drive capability of MOS transistors can be maintained at low power supply voltages by controlling the potential of the bodies of the MOS transistors, as disclosed in xe2x80x9cA Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operationxe2x80x9d, IEDM94, pp. 809-812, 1994. Accordingly, even though a measure is taken to reduce the power supply voltage applied to an SOI CMOS circuit, the circuit speed can be maintained as it is high.
Referring next to FIG. 14, there is illustrated a schematic circuit diagram of a prior art SOI CMOS circuit. The prior art SOI CMOS circuit serves as a NOR gate. In FIG. 14, reference numerals 101 and 102 denote first and second PMOS transistors, respectively, 103 and 104 denote first and second NMOS transistors, respectively, 105 denotes a high reference potential line with a power supply potential connected to a power supply, 106 denotes a low reference potential line with a ground potential connected to ground, A and B denote first and second input terminals to which signals are applied to, respectively, and C denotes an output terminal through which an output signal is furnished.
The prior art SOI CMOS circuit shown in FIG. 14 can maintain a high operating speed even at low power supply voltages by tying the bodies and gates of the first and second PMOS transistors 1 and 2 together, respectively, and by tying the bodies and gates of the first and second NMOS transistors 3 and 4 together, respectively.
While such the prior art SOI CMOS circuit can maintain a high operating speed even at low power supply voltages, it suffers from the following problems. The first problem with the prior art SOI CMOS circuit is that when NMOS transistors have the same size as PMOS transistors, the amount of current flowing in each NMOS transistor is two times as large as that flowing in each PMOS transistor, and an increase in a difference between the carrier mobility of each NMOS transistor and that of each PMOS transistor and hence an increase in a difference between the amount of current flowing in each NMOS transistor and the amount of current flowing in each PMOS transistor result from higher integration of components into the chip and lower power supply voltages, resulting in no margin for the operation of the prior art SOI CMOS circuit, such as a NOR gate, including the PMOS transistors connected in series to each other and hence low noise immunity because of a displacement of the logical threshold voltage of the SOI CMOS circuit, which determines the logic levels of signals, from a voltage intermediate between a power supply potential and a ground potential, as disclosed in FIG. 11 of pp. 153 of Journal of NIKKEI Micro Device issued in September, 1994. Another problem is that since the length of the rising time of output signals furnished by such the prior art SOI CMOS circuit differs considerably from that of their falling time, it is difficult to design and manufacture a high performance LSI circuit which operates with a high degree of reliability.
Although changing the sizes of NMOS and PMOS transistors included in SOI CMOS circuits can be a measure to solve the above problems, this measure causes another problem that the circuit layout increases in complexity because it is difficult to efficiently arrange and wire NMOS and PMOS transistors.
The present invention is made to overcome the above-mentioned problems. It is therefore an object of the present invention to provide an SOI CMOS circuit capable of setting its logical threshold voltage to a voltage having a value in the vicinity of a certain value intermediate between the value of the power supply potential and that of the ground potential.
In accordance with one aspect of the present invention, there is provided an SOI CMOS circuit comprising: a plurality of PMOS transistors connected in series to each other, each of the plurality of PMOS transistors having its body and gate connected to each other; and at least an NMOS transistor connected to one of the plurality of PMOS transistors, the NMOS transistor having its body connected to a low reference potential having a value of ground.
In accordance with a preferred embodiment of the present invention, the SOI CMOS circuit further comprises a plurality of potential limiting circuits each connected between the body and gate of each of the plurality of PMOS transistors, for setting a lower limit of potential of the body of each of the plurality of PMOS transistors to a voltage between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential. Preferably, each of the plurality of potential limiting circuit includes a PMOS transistor having its source connected to the gate of a corresponding one of the plurality of PMOS transistors, and its gate connected to its drain and the body of the corresponding one of the plurality of PMOS transistors.
In accordance with another aspect of the present invention, there is provided an SOI CMOS circuit comprising: a plurality of PMOS transistors connected in series to each other; at least an NMOS transistor connected to one of the plurality of PMOS transistors, the NMOS transistor having its body connected to a low reference potential having a value of ground; and a body potential generating circuit for generating a body potential between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential and for applying the body potential to the bodies of the plurality of PMOS transistor. Preferably, the body potential generating circuit includes a PMOS transistor having its drain connected to its gate and the bodies of the plurality of PMOS transistors.
In accordance with another aspect of the present invention, there is provided an SOI CMOS circuit comprising: a plurality of PMOS transistors connected in series to each other, each of the plurality of PMOS transistor having its body connected to a high reference potential; at least an NMOS transistor connected to one of the plurality of PMOS transistors; and a body potential generating circuit for generating a body potential between a low reference potential having a value of ground and a potential obtained by subtracting a built-in potential from the low reference potential and for applying the body potential to the body of the NMOS transistor. Preferably, the body potential generating circuit includes an NMOS transistor having its drain connected to its gate and the body of the first NMOS transistor.
Further objects and advantages of the present invention will be apparent from the following description of the preferred embodiments of the invention as illustrated in the accompanying drawings.